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products and specifications discussed herein ar e subject to change by micron without notice. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory features pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__1.fm - rev. c 4/ 08 en 1 ?2007 micron technology, inc. all rights reserved. async/page/burst cellularram ? 1.0 memory mt45w512kw16begb features ? single device supports asynchronous, page, and burst operations ? random access time: 70ns ?v cc , v cc q voltages ? 1.7?1.95v v cc ? 1.7?3.6v 1 v cc q ? page mode read access ? 16-word page size ? interpage read access: 70ns ? intrapage read access: 20ns ?burst mode write acce ss: continuous burst ? burst mode read access ? 4, 8, or 16 words or continuous burst ? max clock rate: 104 mhz ( t clk = 9.62ns) ? burst initial latency: 38.5ns (4 clocks) at 104 mhz ? t aclk: 7ns at 104 mhz ?low power consumption ? asynchronous read: <20ma ? intrapage read: <15ma ? intrapage read initial access, burst read: (38.5ns [4 clocks] at 104 mhz) <35ma ? continuous burst read: <28ma ? standby: <65a ? deep power-down (dpd): <10a (typ at 25c) ?low-power features ? partial-array refresh (par) ? dpd mode options designator ?configuration ? 512k x 16 mt45w512kw16be ?package ? 54-ball vfbga (?green?) gb ?access time ? 70ns -70 ?frequency ? 80 mhz 8 ? 104 mhz 1 ?standby power ? standard none figure 1: 54-ball vfbga ball assignment notes: 1. the 3.6v i/o and the ?30c wireless temper- ature exceed the cellularram workgroup 1.0 specification. 2. contact factory for availability. part number example: mt45w512kw16begb-701wt options (continued) designator ? operating temperature range ? wireless (?30c to +85c) 1 wt ? industrial (?40c to +85c) 2 it a b c d e f g h j 1 2 3 4 5 6 top view (ball down) lb# dq8 dq9 v ss q v cc q dq14 dq15 a18 wait oe# ub# dq10 dq11 dq12 dq13 nc a8 clk a0 a3 a5 a17 nc a14 a12 a9 adv# a2 ce# dq1 dq3 dq4 dq5 we# a11 nc cre dq0 dq2 v cc v ss dq6 dq7 nc nc a1 a4 a6 a7 a16 a15 a13 a10 nc
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 4mb_burst_cr1_0_p22ztoc.fm - rev. b 4/ 08 en 2 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory table of contents table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 list of tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 functional block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 ball descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 power-up initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 bus operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 page mode read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 burst mode operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mixed-mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 wait operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 lb#/ub# operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 low-power operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 standby mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 deep power-down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 access using cre . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 software access to the configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 bus configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 burst length (bcr[2:0]) default = continuous burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 burst wrap (bcr[3]) default = burst no wrap (wi thin burst length) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5 output impedance (bcr[5]) defaul t = outputs use full-drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 wait configuration (bcr[8]) default = wait transitions on e clock before data valid/invalid . . . . . . . . .26 wait polarity (bcr[10]) default = wait active high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 latency counter (bcr[13:11]) default = three-clock latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 operating mode (bcr[15]) default = asynchronous operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 refresh configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 partial-array refresh (rcr[2:0]) default = full array refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 deep power-down (rcr[4]) default = dpd disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 page mode operation (rcr[7]) default = disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 typical standby currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 timing requirements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 4mb_burst_cr1_0_p22zlof.fm - rev. b 4/ 08 en 3 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory list of figures list of figures figure 1: 54-ball vfbga ball assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 figure 2: functional block diagra m (512k x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 figure 3: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 figure 4: power-up initialization timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 5: read operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 6: write operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 7: page mode read operation (adv = low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 figure 8: burst mode read (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 figure 9: burst mode write (4-word burst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 10: wired-or wait configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 figure 11: refresh collision during read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 12: refresh collision during write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 figure 13: asynchronous mode configuration register writ e followed by read array operation . . . . . . .18 figure 14: synchronous mode configur ation register write followed by re ad array operation . . . . . . .19 figure 15: asynchronous mode configuration register read followed by read array operation . . . . . . .20 figure 16: synchronous mode configuration register read followed by read array operation . . . . . . . .21 figure 17: load configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 18: read configuration regi ster . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 figure 19: bus configuration register defi nition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 figure 20: wait configuration (bcr[8] = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 21: wait configuration (bcr[8] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 22: wait configuration during burst operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 23: latency counter (variable latency, no refresh collisio n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 24: refresh configuration register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 figure 25: typical refresh current vs. temp erature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 figure 26: ac input/output reference wavefo rm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 27: output load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 figure 28: initialization period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 figure 29: asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 figure 30: asynchronous read using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 figure 31: page mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 figure 32: single-access burst read operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 figure 33: four-word burst read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 figure 34: read burst suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 figure 35: output delay in continuous burst read with bcr[ 8] = 0 for end-of-row condition . . . . . . . . . . .43 figure 36: ce#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 figure 37: lb#/ub#-controlled asyn chronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 figure 38: we#-controlled asynchronous write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 figure 39: asynchronous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 figure 40: burst write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 figure 41: output delay in continuous burst write with bcr[ 8] = 0 for end-of-row condition . . . . . . . . . . . .49 figure 42: burst write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 figure 43: asynchronous write followed by burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 figure 44: asynchronous write followed by bu rst read with adv# low . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 figure 45: burst read followed by asynchro nous write (we#-controlled) . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 figure 46: burst read followed by asynchro nous write using adv# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 figure 47: asynchronous write followed by asynchronous read ? adv# low . . . . . . . . . . . . . . . . . . . . . . . .55 figure 48: asynchronous write followed by asynchronous read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 figure 49: 54-ball vfbga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 4mb_burst_cr1_0_p22zlot.fm - rev. b 4/ 08 en 4 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory list of tables list of tables table 1: vfbga ball descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 table 2: bus operations: asynchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 table 3: bus operations: burst mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 4: sequence and burst length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 table 5: latency configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 6: absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 table 7: electrical characteristics and oper ating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 table 8: deep power-down specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 9: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 table 10: asynchronous read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 table 11: burst read cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 table 12: asynchronous write cycle timing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 table 13: burst write cycle timing requiremen ts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 table 14: initialization timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 5 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory general description general description micron ? cellularram ? is a high-speed, cmos psram memory developed for low- power, portable applications. the mt45w512kw16begb is an 8mb dram core device organized as 512k x 16 bits. this de vice includes an industry-standard burst mode flash interface that dramatically incr eases read/write bandwidth compared with other low-power sram or pseudo-sram (psram) offerings. for seamless operation on a burst flash bus, cellularram products incorporate a trans- parent self refresh mechanism. the hidden re fresh requires no addi tional support from the system memory controller and has no significant impact on device read/write performance. two user-accessible control registers define device operation. the bus configuration register (bcr) defines how the cellularram device interacts with the system memory bus and is nearly identical to its counterpar t on burst mode flash devices. the refresh configuration register (rcr) is used to co ntrol how refresh is performed on the dram array. these registers are automatically load ed with default settings during power-up and can be updated anytime during normal operation. special attention has been focused on standby current consumption during self refresh. this cellularram product includes two system-accessible mechanisms to minimize standby current. partial-array refresh (par) limits refresh to only that part of the dram array that contains essential data. deep power-down (dpd) halts the refresh opera- tion altogether and is used when no vital in formation is stored in the device. these two refresh mechanisms are accessed through the rcr. functional block diagrams figure 2: functional block diagram (512k x 16) note: functional block di agrams illustrate simplified device operation. see the ball description table and timing diagrams for detailed information. a[18:0] ce# we# oe# clk adv# cre wait lb# ub# dq[7:0] dq[15:8] input/ output mux and buffers 512k x 16 dram memory array refresh configuration register (rcr) bus configuration register (bcr) address decode logic control logic
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 6 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory ball descriptions ball descriptions note: the clk and adv# inputs can be tied to v ss if the device is always operating in asynchro- nous or page mode. wait will be asserted, but should be ignored during asynchronous and page mode operations. table 1: vfbga ball descriptions vfbga assignment symbol type description h1, d3, e4, f4, f3, g4, g3, h5, h4, h3, h2, d4, c4, c3, b4, b3, a5, a4, a3 a[18:0] input address inputs : inputs for addresses during read and write operations. addresses are internally la tched during read and write cycles. the address lines are also used to define the value to be loaded into the bcr or the rcr. j2 clk input clock : synchronizes the memory to the system operating frequency during synchronous operations. when configured for synchronous operation, the address is latched on the first rising clk edge when adv# is active. clk is static low or high during asynchronous access read and write operations and during page read access operations. j3 adv# input address valid : indicates that a valid address is present on the address inputs. addresses can be latched on the rising edge of adv# during asynchronous read and write operations. adv# can be held low during asynchronous read and write operations. a6 cre input configuration register enable : when cre is high, writ e operations load the rcr or bcr. b5 ce# input chip enable : activates the device when low. when ce# is high, the device is disabled and goes into standby or dpd mode. a2 oe# input output enable : enables the output buffers when low. when oe# is high, the output buffers are disabled. g5 we# input write enable : determines whether a given cycle is a write cycle. if we# is low, the cycle is a write either to a config uration register or to the memory array. a1 lb# input lower byte enable : dq[7:0]. b2 ub# input upper byte enable : dq[15:8]. g1, f1, f2, e2, d2, c2, c1, b1, g6, f6, f5, e5, d5, c6, c5, b6 dq[15:0] input/ output data inputs/outputs. j1 wait output wait : provides data-valid feed back during burst read and write operations. the signal is gated by ce#. wait is used to arbitrate collisions between refresh and read/write operations. wait is asserted when a burst crosses a row boundary. wait is also used to mask the delay asso ciated with opening a new internal page. wait is asserted and should be ignored during asynchronous and page mode operations. wait is hi gh-z when ce# is high. d6 v cc supply device power supply (1.7?1.95v) : power supply for device core operation. e1 v cc q supply i/o power supply (1.7?3.6v) : power supply for input/output buffers. e6 v ss supply v ss must be connected to ground. d1 v ss q supply v ss q must be connected to ground. e3, g2, h6, j4, j5, j6 nc ? not internally connected.
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 7 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operations bus operations notes: 1. clk must be static high or low during asynchronous read and asynchronous write modes and to achieve standby power during standby and dpd modes. clk must be static (high or low) during burst suspend. 2. the wait polarity is configured throug h the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are af fected. when only lb# is in select mode, dq[7:0] ar e affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, addres s inputs and data inputs /outputs are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (unswitched) to achieve standby current. 7. this device supports cre-con trolled configuration register re ads. this feature is not an official cellularram 1.0 feature. 8. dpd is maintained until rcr is reconfigured. table 2: bus operations: asynchronous mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes read active l l l l h l l low-z data-out 4 write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 configuration register write active l l l h l h x low-z high-z configuration register read active l l l h h h x low-z configuration register out 7 dpd deep power-down l x h x x x x high-z high-z 8
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 8 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operations notes: 1. clk must be static high or low during asynchronous read and asynchronous write modes and to achieve standby power during standby and dpd modes. clk must be static (high or low) during burst suspend. 2. the wait polarity is configured throug h the bus configuration register (bcr[10]). 3. when lb# and ub# are in select mode (low), dq[15:0] are af fected. when only lb# is in select mode, dq[7:0] ar e affected. when only ub# is in the select mode, dq[15:8] are affected. 4. the device will consume active power in this mode whenever addresses are changed. 5. when the device is in standby mode, addres s inputs and data inputs /outputs are internally isolated from any external influence. 6. v in = v cc q or 0v; all device balls must be static (unswitched) to achieve standby current. 7. burst mode operation is initialized through the bus configuration register (bcr[15]). 8. this device supports cre-con trolled configuration register re ads. this feature is not an official cellularram 1.0 feature. 9. dpd is maintained until rcr is reconfigured. table 3: bus operations: burst mode mode power clk 1 adv# ce# oe# we# cre lb#/ ub# wait 2 dq[15:0] 3 notes asynchronous read active l l l l h l l low-z data-out 4 asynchronous write active l l l x l l l low-z data-in 4 standby standby l x h x x l x high-z high-z 5, 6 no operation idle l x l x x l x low-z x 4, 6 initial burst read active l l x h l l low-z x 4, 7 initial burst write active l l h l l x low-z x 4, 7 burst continue active h l x x x l low-z data-in or data-out 4, 7 burst suspend active x x l h x l x low-z high-z 4, 7 configuration register write active l l h l h x low-z high-z 7 configuration register read active l l h h h x low- z configuration register out 7, 8 dpd deep power-down lxhxxxxhigh-zhigh-z 9
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 9 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory part numbering information part numbering information micron cellularram devices ar e available in several differe nt configurations and densi- ties (see figure 3). figure 3: part number chart notes: 1. the 3.6v i/o and the ?3 0c wireless temperature exceed the cellularram workgroup 1.0 specification. valid part number combinations after building the part number using the part numbering chart, visit the micron web site at www.micron.com/psram to verify that the part number is offered and valid. if the device required is not on th is list, contact the factory. device marking due to the size of the package, the micron-standard part number is not printed on the top of the device. instead, an abbreviated devi ce mark consisting of a five-digit alphanu- meric code is used. the abbreviated device marks are cross-referenced to the micron part numbers at the fbga part marking decoder site , www.micron.com/decoder . to find how to locate the abbreviated mark on the device, refer to customer service note csn-11, ?product mark/label,? at www.micron.com/csn . mt 45 w 512k w 16 be gb -70 8 wt es micron technology product family 45 = psram/cellularram memory operating core voltage w = 1.7C1.95v address locations k = kilobits operating voltage w = 1.7C3.6v 1 bus configuration 16 = x16 read/write operation mode be = asynchronous/page/burst package codes gb = 54-ball vfbga green (6 x 9 grid, 0.75mm pitch, 6.0mm x 8.0mm x 1.0mm production status blank = production es = engineering sample ms = mechanical sample operating temperature wt = C30c to +85c (see note 1) it = C40c to +85c (contact factory) standby power options blank = standard frequency 8 = 80 mhz 1 = 104 mhz access/cycle time 70 = 70ns
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 10 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory functional description functional description in general, mt45w512kw16begb devices are hi gh-density alternatives to sram and psram products, popular in low-power, portable applications. the mt45w512kw16begb contains an 8,388,60 8-bit dram core organized as 524,288 addresses by 16 bits. this device implements the same high-speed bus interface found on burst mode flash products. the cellularram bus interface supports both asynchronous and burst mode transfers. page mode accesses are also included as a bandwidth-enhancing extension to the asyn- chronous read protocol. power-up initialization cellularram products include an on-chip volt age sensor used to launch the power-up initialization process. initialization will co nfigure the bcr and the rcr with their default settings (see figure 19 on page 24 and figure 24 on page 28). v cc and v cc q must be applied simultaneously. when v cc and v cc q reach a stable level at or above 1.7v, the device will require 150s to complete its self-initialization process. during the initializa- tion period, ce# should remain high. when initialization is complete, the device is ready for normal operation. figure 4: power-up initialization timing bus operating modes the mt45w512kw16begb cellularram products incorporate a burst mode interface found on flash products targeting low-power, wireless applications. this bus interface supports asynchronous, page mode, and burst mode read and write transfers. the specific interface supported is defined by the value loaded into the bcr. page mode is controlled by the refresh configuration register (rcr[7]). asynchronous mode cellularram products power up in the asyn chronous operating mode. this mode uses the industry-standard sram control bus (c e#, oe#, we#, lb#/ub#). read operations (figure 5 on page 11) are initiated by bringing ce#, oe#, and lb#/ub# low while keeping we# high. valid data will be driven out of the i/os after the specified access time has elapsed. write operations (figure 6 on page 11) occur when ce#, we#, and lb#/ub# are driven low. during asynchronous write operations, the oe# level is a ?don?t care,? and we# will override oe#. the data to be written is latched on the rising edge of ce#, we#, or lb#/ub#, whichever occu rs first. asynchrono us operations (page mode disabled) either can use the adv input to latch the address, or can drive adv low during the entire read/write operation. during asynchronous operation, the clk input must be held static low or high. wait will be driven while the device is enabled, and its state should be ignored. we# low time must be limited to t cem. device ready for normal operation vcc = 1.7v t pu > 150s vccq vcc device initialization
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 11 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operating modes figure 5: read operation (adv = low) note: adv must remain low for page mode operation. figure 6: write operation (adv = low) valid address data ce# don?t care valid data oe# we# lb#/ub# t rc = read cycle time address valid address data ce# don?t care valid data oe# we# lb#/ub# t wc = write cycle time address < t cem
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 12 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operating modes page mode read operation page mode is a performance-enhancing exte nsion to the legacy asynchronous read operation. in page-mode-capable products, an initial asynchronous read access is performed, and then adjacent addresses can be read quickly by simply changing the low-order address. addresses a[3:0] are us ed to determine the members of the 16- address cellularram page. any change in addresses a[4] or higher will initiate a new t aa access time. figure 7 on page 12 shows the timing for a page mode access. page mode takes advantage of the fact that adjacent addresses can be read in a shorter period of time than random addresses. wr ite operations do no t include comparable page mode functionality. during asynchronous page mode operation, the clk input must be held static low or high. ce# must be driven high upon completi on of a page mode access. wait will be driven while the device is enabled, and its st ate should be ignored. page mode is enabled by setting rcr[7] to high. adv must be driven low during all page mode read accesses. the ce# low time is limited by refresh considerations. ce# must not stay low longer than t cem. figure 7: page mode re ad operation (adv = low) burst mode operation burst mode operations enable high-speed synchronous read and write operations. burst operations consist of a multiclock sequence that must be performed in an ordered fashion. after ce# goes low, the address to ac cess is latched on the next rising edge of clk that adv# is low. during this first clock rising edge, we# indicates whether the operation is going to be a read (we# = high, figure 8 on page 13) or a write (we# = low, figure 9 on page 14). the size of a burst can be specified in the bcr as either fixed-length or continuous. fixed-length bursts consist of 4, 8, or 16 wo rds. continuous bursts have the ability to start at a specified address and burst thro ugh the entire memory. the latency count stored in the bcr defines the number of clock cycles that elapse before the initial data value is transferred between the processor and cellularram device. data ce# don?t care oe# we# lb#/ub# address address[0] address[1] address[2] address[3] d[1] d[2] d[3] t aa t apa < t cem t apa t apa d[0]
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 13 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operating modes the wait output will be asserted as soon as ce# goes low and will be deasserted to indicate when data is to be transferred into or out of the memory. wait will again be asserted if the burst crosses the boundary between 128-word rows. when the cellu- larram device has restored the previous row?s data and accessed the next row, wait will be de-asserted and the burst can continue (see figure 35 on page 43). by suspending burst mode, the processor can access other devices without incurring the timing penalty of the initial latency for a ne w burst. bursts are suspended by stopping clk. clk can be stopped high or low. if another device will use the data bus while the burst is suspended, oe# should be taken high to disable the cellularram outputs; otherwise, oe# can remain low. note that the wait output will continue to be active, and, as a result, no other devices should directly share the wait connection to the controller. to continue the burst sequence, oe # is taken low, and then clk is restarted after valid data is available on the bus. the ce# low time is limited by refresh considerations. ce# must not stay low longer than t cem unless row boundaries are crossed at least every t cem. if a burst suspension will cause ce# to remain low for longer than t cem, ce# should be taken high and the burst restarted with a new ce# low/adv# low cycle. figure 8: burst mode read (4-word burst) note: nondefault bcr settings: late ncy code 2 (3 clocks); wait ac tive low; wait asserted during delay. a[18:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# latency code 2 (3 clocks) clk undefined don?t care read burst identified (we# = high) valid address
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 14 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operating modes figure 9: burst mode write (4-word burst) note: nondefault bcr settings: late ncy code 2 (3 clocks); wait ac tive low; wait asserted during delay. mixed-mode operation the device can support a combination of synchronous read and asynchronous write operations when the bcr is configured fo r synchronous operation. the asynchronous write operation requires that the clock (clk) be held static low or high during the entire sequence. the adv# signal can be used to latch the target address, or it can remain low during the entire write operation. ce# must return high when transi- tioning between mixed-mode operations. note that the t cka period is the same as a read or write cycle. this time is required to ensure adequate refresh. mixed-mode operation facilitates a seamless interface to legacy burst mode flash memory controllers (see figure 43 on page 51). a[18:0] d[0] adv# ce# oe# d[1] d[2] d[3] we# wait dq[15:0] lb#/ub# address valid latency code 2 (3 clocks) clk don?t care write burst identified (we# = low)
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 15 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operating modes wait operation the wait output on a cellularram device is typically connected to a shared, system- level wait signal (see figure 10). the shared wait signal is used by the processor to coordinate transactions with multiple memories on the synchronous bus. figure 10: wired-or wait configuration after a read or write operation has been init iated, wait goes active to indicate that the cellularram device requires additional time before data can be transferred. for read operations, wait will remain active until valid data is output from the device. for write operations, wait will indicate to th e memory controller when data will be accepted into the cellularram device. when wa it transitions to an inactive state, the data burst will progress on successive clock edges. during a burst cycle, ce# must remain asserted until the first data is valid. bringing ce# high during this initial latency may cause data corruption. the wait output also performs an arbitratio n role when a read or write operation is launched while an on-chip refresh is in progress. if a collision occurs, wait is asserted for additional clock cycles until the refresh has completed (see figure 11 on page 16 and figure 12 on page 16). when the refresh operation has completed, the read or write operation will continue normally. wait is also asserted when a continuous read or write burst crosses a row boundary. the wait assertion allows time for the new row to be accessed and permits any pending refresh operations to be performed. lb#/ub# operation the lb# enable and ub# enable signals suppor t byte-wide data transfers. during read operations, the enabled byte(s) are driven onto the dq. the dq associated with a disabled byte are put into a high-z state du ring a read operation. during write opera- tions, any disabled bytes will not be transfer red to the ram array, and the internal value will remain unchanged. during an asynchronous write cycle, the data to be written is latched on the rising edge of ce#, we#, lb#, or ub#, whichever occurs first. when both the lb# and ub# are disabled (hig h) during an operation, the device will disable the data bus from receiving or transm itting data. although the device will seem to be deselected, it remains in an ac tive mode as long as ce# remains low. cellularram external pull-up/ pull-down resistor processor ready other device wait other device wait wait
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 16 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory bus operating modes figure 11: refresh collision during read operation note: nondefault bcr settings: latency code 2 (3 clocks); wait active low; wait asserted during delay. figure 12: refresh collision during write operation note: nondefault bcr settings: latency code 2 (3 clocks); wait active low; wait asserted during delay. a[18:0] adv# ce# oe# we# wait dq[15:0] clk v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol d[2] d[1] d[3] valid address additional wait states inserted to allow refresh completion lb#/ub# undefined don?t care d[0] high-z a[18:0] adv# ce# oe# we# wait dq[15:0] clk d[1] d[0] d[3] d[2] valid address additional wait states inserted to allow refresh completion lb#/ub# don?t care v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 17 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory low-power operation low-power operation standby mode operation during standby, the device current consumption is reduced to the level necessary to perform the dram refresh operation. standby operation occurs when ce# is high. the device will enter a reduced power state upon completion of a read or write oper- ation or when the address and control inputs remain static for an extended period of time. this mode will continue until a change occurs to the address or control inputs. deep power-down operation deep power-down (dpd) operation disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been reenabled by rewriting the rcr, the cellularra m device will require 150s to perform an initialization procedure before normal operat ions can resume. during this 150s period, the current consumption will be higher than the specified standby levels, but consider- ably lower than the active current specification. dpd cannot be enabled or disabled by writing to the rcr using the software-access sequence; instead, the rcr should be accessed using cre.
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 18 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers configuration registers two user-accessible configuration registers de fine the device operation. the bus config- uration register (bcr) defines how the cellul arram interacts with the system memory bus and is nearly identical to it s counterpart on burst mode fl ash devices. the refresh configu- ration register (rcr) is used to control how refresh is performed on the dram array. these registers are automatically loaded with default settings during power-up and can be updated any time the devices are operating in a standby state. access using cre the configuration registers are loaded either using a synchronous or an asynchronous write operation when the configuration re gister enable (cre) input is high (see figure 13 on page 18 and figure 14 on page 19). when cre is low, a read or write operation will access the memory array. the register values are placed on address pins a[18:0]. in an asynchronous write, the values are latched into the configuration register on the rising edge of adv#, ce#, or we#, whichever occurs first; lb# and ub# are ?don?t care.? the bcr is accessed when a[17] is high; the rcr is accessed when a[17] is low. for reads, address inputs other than a17 are ?don?t care,? and register bits 15:0 are output on dq[15:0]. figure 13: asynchronous mode configuration re gister write followed by read array operation notes: 1. a[17] = low to load rcr; a[17] = high to load bcr. a[18:0] (except [a17]) opcode address address valid data a[17] 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate control register access write address bus value to control register cre t avs t avh t avh t avs t vp t vph t cph t wp t cw don?t care select control register
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 19 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers figure 14: synchronous mode configuration regi ster write followed by read array operation notes: 1. nondefault bcr settings for cr write in synchronous mode followed by read array operation: latency code 2 (3 clocks); wa it active low; wait asserted during delay. 2. a[17] = low to load rcr; a[17] = high to load bcr. 3. ce# must remain low to complete a burst-of -one write. wait must be monitored?addi- tional wait cycles caused by refresh collis ions require a corresponding number of addi- tional ce# low cycles. clk a[18:0] (except [a17]) a[17] 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t csp t sp t hd high-z opcode address high-z t cew latch control register value latch control register address t cbph 3 valid data address don?t care
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 20 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers figure 15: asynchronous mode configuration re gister read followed by read array operation notes: 1. a[17] = low to load rcr; a[17] = high to load bcr. a[18:0] (except a[17]) address address valid data valid cr a[17] 1 adv# ce# oe# we# lb#/ub# dq[15:0] initiate register access cre t avh t avs t aa t vp t vph t cbph t co t olz t ba t lz t oe t lz undefined don?t care select register t aadv t avs t aa t hz t ohz t bhz t avh
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 21 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers figure 16: synchronous mode configuration re gister read followed by read array operation notes: 1. nondefault bcr settings for synchronou s mode register read followed by read array operation: latency code 2 (3 clocks); wa it active low; wait asserted during delay. 2. a[17] = low to load rcr; a[17] = high to load bcr. 3. ce# must remain low to complete a burst- of-one read. wait must be monitored?addi- tional wait cycles caused by refresh coll isions require a corr esponding number of additional c e# low cycles. clk a[18:0] (except a[17]) a[17] 2 cre adv# ce# oe# we# lb#/ub# wait dq[15:0] t sp t sp t sp t hd t hd t hd t hz t csp t koh undefined don?t care t sp t hd address t cew latch control register value t olz latch control register address t cbph 3 t boe valid data address t aclk t ohz high-z high-z t aba valid cr
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 22 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers software access to the configuration register software access of the configuration registers uses a sequence of asynchronous read and asynchronous write operations. the conten ts of the configuration registers can be read or modified using the software sequence. the configuration registers are loaded using a four-step sequence consisting of two asynchronous read operations followed by two asynchronous write operations (see figure 17). the read sequence is virtually iden tical except that an asynchronous read is performed during the fourth operation (see figure 18 on page 23). note that a third read cycle of the highest address will cancel the access sequence until a different address is read. the address used during all read and write operations is the highest address of the cellularram device being accessed (7ffffh); the content at this address is not changed by using this sequence. the data value presented during the third operation (write) in the sequence defines whether the bcr or the rcr is to be accessed . if the data is 0000h, the sequence will access the rcr; if the data is 0001h, the se quence will access the bcr. during the fourth operation, dq[15:0] transfer data into or out of bits 15?0 of the configuration registers. the use of the software sequence does not affect the ability to perform the standard (cre-controlled) method of loading the conf iguration registers. however, the software nature of this access mechanism eliminates the need for the control register enable (cre) pin. if the software mechanism is used, the cre pin can simply be tied to v ss . the port line often used fo r cre control purposes is no longer required. figure 17: load configuration register notes: 1. it is possible that the data stored at the highest memory locati on will be altered if the data at the falling edge of we# is not 0000h or 0001h. address (max) address (max) address (max) xxxxh xxxxh rcr: 0000h bcr: 0001h cr value in address ce# oe# we# lb#/ub# data don?t care read read write write address (max) 0ns (min) note 1
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 23 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers figure 18: read configuration register notes: 1. it is possible that the data stored at the highest memory locati on will be altered if the data at the falling edge of we# is not 0000h or 0001h. address (max) address (max) address (max) xxxxh xxxxh cr value out address ce# oe# we# lb#/ub# data don?t care read read write read rcr: 0000h bcr: 0001h address (max) 0ns (min) note 1
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 24 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers bus configuration register the bcr defines how the cellularram device interacts with the system memory bus. page mode operation is enabled by a bit contained in the rcr. figure 19 defines the control bits in the bcr. at power-up, the bcr is set to 9d4fh. the bcr is accessed using cre and a[17] high or through the configuration register software sequence with dq = 0001h on the third cycle. figure 19: bus configuration register definition notes: 1. all burst writes are continuous. a13 13 12 11 0 latency counter 3 21 wait polarity 4 5 wait configuration (wc) clock configuration (cc) 6 7 8 output impedance burst wrap (bw) 1 14 a12a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 1 operating mode synchronous burst access mode asynchronous access mode (default) bcr[12] bcr[11] latency counter bcr[13] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 code 0?reserved code 1?reserved code 2 code 3 (default) code 4?reserved code 5?reserved code 6?reserved code 7?reserved 0 1 wait polarity active low active high (default) bcr[10] 0 1 wait configuration asserted during delay asserted one data cycle before delay (default) 0 1 output impedance full drive (default) 1/4 drive bcr[5] burst wrap (note 1) burst wraps within the burst length burst no wrap (default) bcr[3] bcr[1] bcr[0] burst length (note 1) bcr[2] 15 burst length (bl) 1 reserved reserved 9 10 reserved operating mode reserved a14 a15 a16 0 1 register select select rcr select bcr must be set to "0" 17 16 register select a17 reserved must be set to "0" must be set to "0" must be set to "0" must be set to "0" bcr[8] 0 1 clock configuration not supported rising edge (default) bcr[6] bcr[15] bcr[17] 0 1 0 0 0 1 0 1 1 1 1 0 1 1 4 words 8 words 16 words continuous burst (default) reserved a18 18 must be set to "0"
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 25 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers burst length (bcr[2:0]) default = continuous burst burst lengths define the number of words th e device outputs during a burst read oper- ation. the device supports a burst length of 4, 8, or 16 words. the device can also be set in continuous burst mode where data is output sequentially without regard to address boundaries; the internal address wraps to 00 000h if the device is read past the last address. write bursts are always pe rformed using continuous burst mode. burst wrap (bcr[3]) default = burst no wrap (within burst length) the burst wrap option determines whether a 4-, 8-, or 16-word burst read wraps within the burst length or steps through sequential ad dresses. if the wrap option is not enabled, the device outputs data from sequential ad dresses without regard to burst boundaries; the internal address wraps to 00000h if th e device is read past the last address. table 4: sequence and burst length burst wrap starting address 4-word burst length 8-word burst length 16-word burst length continuous burst bcr[3] wrap (decimal) linear linear linear linear 0 yes 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6 -7-8-9-10-11-12-13-14-15 0-1-2-3-4-5-6-? 1 1-2-3-0 1-2-3-4-5-6-7-0 1-2-3-4-5-6-7-8 -9-10-11-12-13-14-15-0 1-2-3-4-5-6-7-? 2 2-3-0-1 2-3-4-5-6-7-0-1 2-3-4-5-6-7-8-9 -10-11-12-13-14-15-0-1 2-3-4-5-6-7-8-? 3 3-0-1-2 3-4-5-6-7-0-1-2 3-4-5-6-7-8-9- 10-11-12-13-14-15-0-1-2 3-4-5-6-7-8-9-? 4 4-5-6-7-0-1-2-3 4-5-6-7-8-9-10-11-12 -13-14-15-0-1-2-3 4-5-6-7-8-9-10-? 5 5-6-7-0-1-2-3-4 5-6-7-8-9-10-11-12- 13-14-15-0-1-2-3-4 5-6-7-8-9-10-11-? 6 6-7-0-1-2-3-4-5 6-7-8-9-10-11-12-13- 14-15-0-1-2-3-4-5 6-7-8-9-10-11-12-... 7 7-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14- 15-0-1-2-3-4-5-6 7-8-9-10-11-12-13-? ... ... ... 14 14-15-0-1-2-3-4-5-6-7-8-9-10 -11-12-13 14-15-16-17-18-19-20- ... 15 15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14 15-16-17-18-19-20-21- ... 1 no 0 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6- 7-8-9-10-11-12-13-14- 15 0-1-2-3-4-5-6-? 1 1-2-3-4 1-2-3-4-5-6-7-8 1-2-3-4-5-6-7-8 -9-10-11-12-13-14-15-16 1-2-3-4-5-6-7-? 2 2-3-4-5 2-3-4-5-6-7-8-9 2-3-4-5 -6-7-8-9-10-11-12-13-14-15-16- 17 2-3-4-5-6-7-8-? 3 3-4-5-6 3-4-5-6-7-8-9-10 3-4-5-6- 7-8-9-10-11-12-13-14-15-16-17- 18 3-4-5-6-7-8-9-? 4 4-5-6-7-8-9-10-11 4-5-6-7-8- 9-10-11-12-13-14-15-16-17- 18-19 4-5-6-7-8-9-10-? 5 5-6-7-8-9-10-11-12 5-6-7-8-9- 10-11-12-13-14-15-16-17-18- 19-20 5-6-7-8-9-10-11-? 6 6-7-8-9-10-11-12-13 6-7-8-9- 10-11-12-13-14-15-16-17-18-19- 20-21 6-7-8-9-10-11-12-? 7 7-8-9-10-11-12-13- 14 7-8-9-10-11-12-13-14-...-17-18-19-20-21- 22 7-8-9-10-11-12-13-? ... ... ... 14 14-15-16-17-18-19-...-23-24-25-26-27- 28-29 14-15-16-17-18-19-20- ? 15 15-16-17-18-19-20-...-24-25-26-27-28- 29-30 15-16-17-18-19-20-21- ?
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 26 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers output impedance (bcr[ 5]) default = outputs use full-drive strength the output driver strength can be altered to adjust for different data bus loading scenarios. the reduced-strength option should be more than adequate in stacked chip (flash + cellularram) environments when there is a dedicated memory bus. the reduced- drive-strength option is included to minimize noise generated on the data bus during read operations. normal output impedance sh ould be selected when using a discrete cellularram device in a more heavily loaded data bus environment. partial drive is approximately one-quarter-full drive streng th. outputs are config ured at full-drive strength during testing. wait configuration (bcr[8]) default = wait tran sitions one clock before data valid/invalid the wait configuration bit is used to de termine when wait transitions between the asserted and the deasserted state with respect to valid data presented on the data bus. the memory controller will use the wait si gnal to coordinate data transfer during synchronous read and write operations. when bc r[8] = 0, data will be valid or invalid on the clock edge immediately after wait transi tions to the deasserted or asserted state, respectively (see figure 20 and figure 22 on page 27). when bcr[8] = 1, the wait signal transitions one clock period prior to the data bus going valid or invalid (see figures 21 and figure 22 on page 27). figure 20: wait configuration (bcr[8] = 0) note: data valid/invalid immedi ately after wait transitions (b cr[8] = 0). see figure 22 on page 27. figure 21: wait configuration (bcr[8] = 1) note: valid/invalid data delayed for one clock after wait transitio ns (bcr[8] = 1). see figure 22 on page 27. wait dq[15:0] clk data[0] data[1] data immediately valid (or invalid) high-z wait d[15:0] clk data[0] data valid (or invalid) after one clock delay high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 27 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers figure 22: wait configuration during burst operation note: nondefault bcr setting for wait duri ng burst operation: wait active low. wait polarity (bcr[10]) default = wait active high the wait polarity bit indicates whether an asserted wait output should be high or low. this bit will determine whether the wait signal requires a pull-up or pull-down resistor to maintain the deasserted state. latency counter (bcr[13:11]) default = three-clock latency the latency counter bits determine how many clocks occur between the beginning of a read or write operation and the first data value transferred. only latency code 2 (3 clocks) or latency code 3 (4 clocks ) is allowed (see table 5 and figure 23). operating mode (bcr[15]) default = asynchronous operation the operating mode bit either selects sy nchronous burst operation or the default asynchronous mode of operation. figure 23: latency counter (varia ble latency, no refresh collision) table 5: latency configuration latency configuration code max input clk frequency 104 mhz 80 mhz 2 (3 clocks) 66 (15ns) 53 (18.75ns) 3 (4 clocks) ? default 104 (9.62ns) 80 (12.5ns) wait wait dq[15:0] clk d[0] d[1] bcr[8] = 0 data valid in current cycle bcr[8] = 1 data valid in next cycle don?t care d[2] d[3] d[4] a[18:0] adv# dq[15:0] clk code 2 valid output valid output valid output valid output valid output valid output valid output valid output valid output code 3 (default) dq[15:0] dont care undefined v ih v il v ih v il v ih v il v oh v ol v oh v ol valid address
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 28 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory configuration registers refresh configuration register the refresh configuration register (rcr) defines how the cellularram device performs its transparent self refresh. altering the refresh parameters can dramatically reduce current consumption during standby mode. page mode control is also embedded into the rcr. figure 24 describes the control bits used in the rcr. at power-up, the rcr is set to 0010h. the rcr is accessed using cre and a[17] low or through the configuration register software-access sequence with dq = 0000h on the third cycle (see ?configuration regis- ters? on page 18). partial-array refresh (rcr[2:0] ) default = full array refresh the par bits restrict refresh operation to a po rtion of the total memory array. the refresh options are full array or none of the array. figure 24: refresh configuration register mapping notes: 1. other settings result in full-array refresh coverage. deep power-down (rcr[4]) default = dpd disabled the deep power-down bit enables and disables all refresh-related activity. this mode is used if the system does not require the storage provided by the cellularram device. any stored data will become corrupted when dpd is enabled. when refresh activity has been reenabled, the cellularram device will require 150s to perform an initialization proce- dure before normal operations can resume. deep power-down is enabled when rcr[4] = 0 and remains enabled until rcr[4] is set to ?1.? dpd should not be enabled or disabled with the software-access sequence; instead, use cre to access the rcr. page mode operation (rcr[7]) default = disabled the page mode operation bit determines wh ether page mode is enabled for asynchro- nous read operations. in the power-up default state, page mode is disabled. par 1 a4 a3 a2 a1 a0 address bus 4 5 1 2 3 0 reserved reserved 6 a5 0 1 deep power-down dpd enable dpd disable (default) rcr[4] reserved a6 all must be set to "0" all must be set to "0" a16?a8 16?8 17 register select a17 0 1 register select select rcr select bcr rcr[17] rcr[1] 0 rcr[0] 0 refresh coverage full array (default) rcr[2] 0 00 1 none of array dpd must be set to "0" a7 7 page 0 1 page mode enable/disable page mode disabled (default) page mode enable rcr[7] reserved a18 18 must be set to "0"
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 29 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory electrical characteristics electrical characteristics stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condit ions for extended periods may affect reli- ability. notes: 1. ?30c exceeds the cellularram workgroup 1.0 specification of ?25c. table 6: absolute maximum ratings parameter rating voltage to any ball except v cc ; v cc q relative to v ss ?0.5v to (4.0v or v cc q + 0.3v, whichever is less) voltage on v cc supply relative to v ss ?0.2v to +2.45v voltage on v cc q supply relative to v ss ?0.2v to +4.0v storage temperature (plastic) ?55oc to +150oc operating temperature (case) wireless 1 industrial ?30oc to +85oc ?40oc to +85oc soldering temper ature and time 10 seconds (solder ball only) +260oc
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 30 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory electrical characteristics notes: 1. the 3.6v i/o and the ?3 0c wireless temperature exceed the cellularram workgroup 1.0 specification of ?25c. 2. input signals may overshoot to v cc q + 1.0v for periods less than 2ns during transitions. 3. v ih (min) value is not aligned with cellula rram workgroup 1.0 specification of v cc q - 0.4v. 4. input signals ma y undershoot to v ss - 1.0v for periods less than 2ns during transitions. 5. bcr[5] = 0b. 6. this parameter is specified with the outputs di sabled to avoid external loading effects. the user must add the current required to drive out put capacitance expected in the actual sys- tem. 7. i sb (max) values measured with par set to full array. to achieve low standby current, all inputs must be driven either to v cc q or v ss . i sb might be slightly hi gher for up to 500ms after power-up, after changes to the par array partition, or when entering standby mode. table 7: electrical characteristics and operating conditions wireless temperature 1 (?30oc < t c < +85oc); industrial temperature (?40oc < t c < +85oc) description conditions symbol min max unit notes supply voltage v cc 1.7 1.95 v i/o supply voltage v cc q1.73.6v input high voltage v ih v cc q - 0.4 v cc q + 0.2 v 2, 3 input low voltage v il ?0.2 0.4 v 4 output high voltage i oh = ?0.2ma v oh 0.8 v cc q? v5 output low voltage i ol = +0.2ma v ol ? 0.2 v cc qv 5 input leakage current v in = 0 to v cc qi li ?1a output leakage current oe# = v ih or chip disabled i lo ?1a operating current symbol typ max unit notes asynchronous random read/ write v in = v cc q or 0v chip enabled, i out = 0 i cc 1?70 ? 20ma6 ? asynchronous page read i cc 1p ?70 ? 15 ma 6 ? initial access, burst read/write i cc 2 104 mhz ? 35 ma 6 80 mhz 30 continuous burst read i cc 3r 104 mhz ? 28 ma 6 80 mhz 22 continuous burst write i cc 3w 104 mhz ? 33 ma 6 80 mhz 25 standby current v in = v cc q or 0v ce# = v cc q i sb standard ? 65 a 7
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 31 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory electrical characteristics typical standby currents the following figure refers to typical standby currents for the device. figure 25: typical refresh current vs. temperature note: typical i sb currents for each par setting. C45 C35 C25 C15 C5 5 15 25 35 45 55 65 75 85 95 45 40 35 30 25 20 15 10 5 0 temperature (c) i sb (a) par = full par = 0
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 32 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory electrical characteristics notes: 1. these parameters are verified in device characterization and are not 100% tested. figure 26: ac input/output reference waveform notes: 1. ac test inputs are driven at v cc q for a logic 1 and v ss q for a logic 0. input rise and fall times (10% to 90%) <1.6ns. 2. input timing begins at v cc q/2. 3. output timing ends at v cc q/2. figure 27: output load circuit notes: 1. all tests are performed with the outputs co nfigured for full-drive strength (bcr[5] = 0b). table 8: deep power-down specifications description conditions symbol typ unit deep power-down v in = v cc q or 0v; +25c i zz 10 a table 9: capacitance description conditions symbol min max unit notes input capacitance t c = +25oc; f = 1 mhz; v in = 0v c in 2.0 6.5 pf 1 input/output capacitance (dq) c io 3.0 6.5 pf 1 output test points input 1 v cc q v ss q v cc q/2 3 v cc q/2 2 dut vccq/2 30pf test point 50
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 33 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing requirements timing requirements notes: 1. all tests are performed with the outputs co nfigured for full-drive strength (bcr[5] = 0b). 2. low-z to high-z timings are tested with the circuit shown in figure 27 on page 32. the high-z timings measure a 100mv transition either from v oh or v ol toward v cc q/2. 3. high-z to low-z timi ngs are tested with the circuit shown in figure 27 on page 32. the low- z timings measure a 100mv trans ition away from the high-z (v cc q/2) level either toward v oh or v ol . 4. page mode en abled only. table 10: asynchronous read cycle timing requirements parameter 1 symbol 70ns unit notes min max address access time t aa ? 70 ns adv# access time t aadv ? 70 ns page access time t apa ? 20 ns address hold from adv# high t avh 5 ? ns address setup to adv# high t avs 5 ? ns lb#/ub# access time t ba ? 70 ns lb#/ub# disable to dq high-z output t bhz ? 8 ns 2 lb#/ub# enable to low-z output t blz 10 ? ns 3 maximum ce# pulse width t cem ? 8 s 4 ce# low to wait valid t cew 1 7.5 ns chip select access time t co ? 70 ns ce# low to adv# high t cvs 10 ? ns chip disable to dq and wait high-z output t hz ? 8 ns 2 chip enable to low-z output t lz 10 ? ns 3 output enable to valid output t oe ? 20 ns output hold from address change t oh 5 ? ns output disable to dq high-z output t ohz ? 8 ns 2 output enable to low-z output t olz 3 ? ns 3 page cycle time t pc 20 ? ns read cycle time t rc 70 ? ns adv# pulse width low t vp 10 ? ns adv# pulse width high t vph 10 ? ns
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 34 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing requirements notes: 1. all tests are performed with the outputs co nfigured for full-drive strength (bcr[5] = 0b). 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: clocked ce# high or ce# high for greater than 15ns. 3. low-z to high-z timings are tested with the circuit shown in figure 27 on page 32. the high-z timings measure a 100mv transition either from v oh or v ol toward v cc q/2. 4. high-z to low-z timings are tested with the circuit shown in figure 27 on page 32. the low-z timings measure a 100mv tra nsition away from the high-z (v cc q/2) level either toward v oh or v ol . table 11: burst read cycle timing requirements parameter 1 symbol 104 mhz 80 mhz unit notes min max min max burst to read access time t aba ? 35.9 ? 46.5 ns clk to output delay t aclk ? 7 ? 9 ns burst oe# low to output delay t boe ? 20 ? 20 ns ce# high between subsequent burst and mixed-mode operations t cbph5?5?ns2 maximum ce# pulse width t cem ? 8 ? 8 s ce# low to wait valid t cew 1 7.5 1 7.5 ns clk period t clk 9.62 ? 12.5 ? ns ce# setup time to active clk edge t csp 3 ? 4.5 ? ns hold time from active clk edge t hd 2?2?ns chip disable to dq and wait high-z output t hz ? 8 ? 8 ns 3 clk rise or fall time t khkl ? 1.6 ? 1.8 ns clk to wait valid t khtl ? 7 ? 9 ns output hold from clk t koh 2?2?ns clk high or low time t kp 3?4?ns output disable to dq high-z output t ohz ? 8 ? 8 ns 3 output enable to low-z output t olz 3 ? 3 ? ns 4 setup time to active clk edge t sp 3?3?ns
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 35 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing requirements notes: 1. high-z to low-z timings are tested with the circuit show n in figure 27 on page 32. the low-z timings measure a 100mv tra nsition away from the high-z (v cc q/2) level either toward v oh or v ol . 2. low-z to high-z timings are tested with the circuit shown in figure 27 on page 32. the high-z timings measure a 100mv transition either from v oh or v ol toward v cc q/2. 3. we# low time must be limited to t cem (8s). table 12: asynchronous write cycle timing requirements parameter symbol 70ns unit notes min max address and adv# low setup time t as 0 ? ns address hold from adv# going high t avh 5 ? ns address setup to adv# going high t avs 5 ? ns address valid to end of write t aw 70 ? ns lb#/ub# select to end of write t bw 70 ? ns ce# low to wait valid t cew 1 7.5 ns asynchronous address- to-burst transition time t cka 70 ? ns ce# high between subsequent asynchronous operations t cph 5 ? ns ce# low to adv# high t cvs 10 ? ns chip enable to end of write t cw 70 ? ns data hold from write time t dh 0 ? ns data write setup time t dw 23 ? ns chip disable to wait high-z output t hz ? 8 ns chip enable to low-z output t lz 10 ? ns 2 end write to low-z output t ow 5 ? ns 1 adv# pulse width t vp 10 ? ns adv# pulse width high t vph 10 ? ns adv# setup to end of write t vs 70 ? ns write cycle time t wc 70 ? ns write to dq high-z output t whz ? 8 ns 2 write pulse width t wp 46 ? ns 3 write pulse width high t wph 10 ? ns write recovery time t wr 0 ? ns
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 36 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing requirements notes: 1. when configured for synchronous mode (b cr[15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfi ed by either of the following two conditions: clocked ce# high or ce# high for greater than 15ns. figure 28: initialization period table 13: burst write cycle timing requirements parameter symbol 104 mhz 80 mhz unit notes min max min max ce# high between subsequent burst and mixed-mode operations t cbph 5 ? 5 ? ns 1 minimum ce# pulse width t cem ? 8 ? 8 s 1 ce# low to wait valid t cew17.517.5ns clock period t clk 9.62 ? 12.5 ? ns ce# setup to clk active edge t csp3 ?4.5?ns hold time from active clk edge t hd 2 ? 2 ? ns chip disable to wait high-z output t hz?8?8ns clk rise or fall time t khkl ? 1.6 ? 1.8 ns clock to wait valid t khtl?7?9ns clk high or low time t kp 3 ? 4 ? ns setup time to active clk edge t sp 3 ? 3 ? ns table 14: initialization timing parameters parameter symbol -70 unit min max initialization period (require d before normal operations) t pu ? 150 s t pu vcc, vccq = 1.7v vcc (min) device ready for normal operation
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 37 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams timing diagrams figure 29: asynchronous read v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol a[18:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aa t hz t ba high-z high-z t rc t co t bhz t ohz t oe t cew t hz valid output high-z undefined don?t care t blz t lz t olz
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 38 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 30: asynchro nous read using adv# a[18:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t vph t aadv t aa t vp t hz t ba high-z high-z t cvs t co t blz t bhz t ohz t lz t oe t olz valid output t avh t avs high-z undefined don?t care t cew t hz v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 39 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 31: page mode read a[3:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] valid address t aa t hz t ba high-z high-z t co t cem t blz t bhz t ohz t lz t oe t olz t cew t hz high-z undefined don?t care a[18:4] valid address valid address valid address valid address t rc valid output t apa t pc v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol t oh valid output valid output valid output
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 40 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 32: single-access burst read operation notes: 1. nondefault bcr settings for single-access burst read operation: latency code 2 (3 clocks); wait active low; wait asserted during delay. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aba valid output valid address high-z t koh t ohz t sp t hd lb#/ub# v ih v il t csp t sp t cem t olz t hd t hz t kp t kp t khkl t hd t sp undefined don?t care read burst identified (we# = high) t khtl t boe high-z high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 41 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 33: four-word burst read operation notes: 1. nondefault bcr settings for 4-word burst read operation: latency code 2 (3 clocks); wait active low; wait asserted during delay. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t clk t khkl t hd valid address high-z t koh t hz t hd t sp t hd lb#/ub# v ih v il t olz t cbph t csp t sp t cem t sp t hd t ohz t kp t kp undefined don?t care read burst identified (we# = high) t cew t aclk t khtl valid output valid output valid output valid output t boe high-z t aba high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 42 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 34: read burst suspend notes: 1. nondefault bcr settings for read burst suspend: latency code 2 (3 clocks); wait active low; wait asserted during delay. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t sp t hd t olz t aclk lb#/ub# v ih v il t clk t sp t hd t csp t sp t cem t sp t hd t koh valid output valid address t cbph t hz t ohz valid output valid output valid output valid output t boe t ohz t boe valid address high-z don?t care undefined high-z valid output t olz high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 43 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 35: output delay in continuous burst read with bcr[8] = 0 for end-of-row condition notes: 1. nondefault bcr settings for continuous bu rst read showing an output delay, bcr[8] = 0 for end-of-row condition: latency code 2 (3 clocks); wait active low; wait asserted during delay. 2. wait will be asserted a maximu m of (lc) cycles (bcr[8] = 0; wait asserted during delay). lc = latency co de (bcr[13:11]). 3. ce# must not remain low longer than t cem. t aclk t koh a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v oh v ol t khtl t khtl t clk lb#/ub# v ih v il valid output valid output valid output valid output note 2 note 3 don?t care
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 44 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 36: ce#-controlled asynchronous write a[18:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in valid address high-z high-z t wc t cew t hz valid input t aw don?t care t wr t cw t dw dq[15:0] out t whz t bw t lz t dh t as t wp t wph v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v oh v ol high-z t cph
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 45 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 37: lb#/ub#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[18:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z t wc t cew t hz valid input t aw don?t care t wr t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t dh t as t wp t wph high-z high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 46 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 38: we#-controlled asynchronous write v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[18:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address t wc t cew t hz valid input t aw don?t care t wr t dw dq[15:0] out v oh v ol t whz t bw t cw t lz t wp t dh t ow t as t wph high-z high-z high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 47 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 39: asynchronous write using adv# v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol a[18:0] adv# ce# lb#/ub# oe# we# wait dq[15:0] in v ih v il valid address high-z high-z t cew t hz valid input t vs don?t care t cw t dw dq[15:0] out v oh v ol t whz t bw t lz t wp t dh t ow t as t wph t as t vph t avh t avs t vp t aw high-z
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 48 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 40: burst write operation notes: 1. nondefault bcr settings fo r burst write operation: latency co de 2 (3 clocks); wait active low; wait asserted. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t clk t kp t sp t hd t csp t cem d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp t hd t sp high-z high-z lb#/ub# v ih v il t sp t hd t hd don?t care write burst identified (we# = low) t cbph t khtl t hz t cew t kp t khkl
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 49 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 41: output delay in continuous burst write with bcr[8] = 0 for end-of-row condition notes: 1. nondefault bcr settings fo r continuous burst write, bcr[8] = 0; wait active low; wait asserted during delay. do not cross row boundaries with fixed latency. 2. ce# must not remain low longer than t cem. 3. wait asserts anywhere from lc to 2lc cycles. lc = latenc y code (bcr[13:11]). 4. taking ce# high or adv# low on the start-of -row cycle will abort the burst and not write the start-of-row data. devices from different cellularram vendors can assert wait so that the start-of-row data is input just before (as sh own) or just after wait asserts. this differ- ence in behavior will not be noticed by contro llers that monitor wait or that use wait to abort on the start-of-row input cycle. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] v oh v ol clk v ih v il v ih v il t khtl t khtl t clk t sp t hd valid input valid input start of row (a[6:0] = 00h) (note 4) end of row (a[6:0] = 7fh) note 3 note 4 valid input valid input don?t care v ih v il lb#/ub#
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 50 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 42: burst write followed by burst read notes: 1. nondefault bcr settings for burst write followed by burst re ad: latency code 2 (3 clocks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: clocked ce# hi gh or ce# high for greater than 15n s. note that the cellularram workgroup 1.0 specification requires ce# to be clocked high to terminate the burst. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il t clk t sp t sp t hd t csp d[3] d[2] d[1] d[0] valid address t hd t sp t hd t sp t hd valid address t aba t csp t sp t ohz t koh valid output valid output valid output valid output high-z high-z v oh v ol lb#/ub# v ih v il t hd t sp t hd t sp t hd t sp t hd high-z undefined don?t care t boe t cbph 2 high-z t sp t hd t aclk
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 51 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 43: asynchronous wr ite followed by burst read notes: 1. nondefault bcr se ttings for asynch ronous write followed by burst read: latency code 2 (3 clocks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: clocked ce# hi gh or ce# high for greater than 15n s. note that the cellularram workgroup 1.0 specification requires ce# to be clocked high to terminate the burst. t clk t sp t hd t sp t hd valid address t ohz t koh t aclk high-z high-z t avs t avh t aw t wr t vp t vs t cka a[18:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t as t as t wp t wc t dh t dw data data high-z t cvs t sp t cew t sp t hd t csp t wc t wc t bw t whz valid output valid output valid output valid output don?t care undefined t aba t boe t cbph 2 t vph valid address valid address
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 52 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 44: asynchronous write foll owed by burst read with adv# low notes: 1. nondefault bcr se ttings for asynch ronous write followed by burst read: latency code 2 (3 clocks); wait active low; wait asserted during delay. 2. when configured for synchronous mode (bcr [15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: clocked ce# hi gh or ce# high for greater than 15n s. note that the cellularram workgroup 1.0 specification requires ce# to be clocked high to terminate the burst. t clk t sp t hd t sp t hd valid address t ohz t koh t aclk high-z high-z t avs t avh t aw t wr t vp t vs t cka a[18:0] v ih v il adv# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v ih v il v oh v ol ce# v ih v il lb#/ub# v ih v il t cw t wph t as t as t wp t wc t dh t dw data data high-z t cvs t sp t cew t sp t hd t csp t wc t wc t bw t whz valid output valid output valid output valid output don?t care undefined t aba t boe t cbph 2 t vph valid address valid address
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 53 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 45: burst read followed by asynchronous write (we#-controlled) notes: 1. when configured for synchronous mode (b cr[15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: clocked ce# hi gh or ce# high for greater than 15ns. note that cellularram workgroup specification 1.0 requires ce# to be clocked high to terminate the burst. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v oh v ol t sp t clk t aclk t cew t hd t aba t aw t cw t wr valid output valid address high-z t koh t dw t ohz t sp t hd lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t hz t bw t sp t hz t hd t sp undefined don?t care read burst identified (we# = high) t wc t khtl valid address valid input high-z t cew t cbph 1 t boe
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 54 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 46: burst read followed by asynchronous write using adv# notes: 1. when configured for synchronous mode (b cr[15] = 0), a refresh opportunity must be pro- vided every t cem. a refresh opportunity is satisfied by either of the following two condi- tions: clocked ce# hi gh or ce# high for greater than 15ns. note that cellularram workgroup specification 1.0 requires ce# to be clocked high to terminate the burst. a[18:0] v ih v il adv# v ih v il ce# v ih v il oe# v ih v il we# v ih v il wait dq[15:0] in/out v oh v ol clk v ih v il v oh v ol t sp t clk t cew t hd t vph t vs t avs t avh t aw t cw valid output valid address high-z t koh t dw t ohz t sp t hd t vp lb#/ub# v ih v il t csp high-z t olz t hd t wp t wph t as t dh t bw t sp t hz t hd t sp undefined don?t care read burst identified (we# = high) valid address valid input high-z t cew t hz t cbph 1 t aclk t boe t as t khtl t aba
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 55 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 47: asynchronous write follow ed by asynchronous read ? adv# low notes: 1. when configured for synchronous mode (b cr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the ap propriate internal refresh operation. otherwise, t cph is only required after ce#-controlled writes. valid address valid address a[18:0] v ih v il adv# v ih v il oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# v ih v il v ih v il v ih v il v ih v il t cw t wph t wp t wc t dh t dw t hz data t hz high-z valid address t aa t bhz t cph 1 t co valid output high-z t oe t olz t lz t blz t ohz t hz t aw t wr t bw don?t care undefined data
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 56 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory timing diagrams figure 48: asynchronous write followed by asynchronous read notes: 1. when configured for synchronous mode (b cr[15] = 0), ce# must remain high for at least 5ns ( t cph) to schedule the ap propriate internal refresh operation. otherwise, t cph is only required after ce#-controlled writes. valid address valid address t avs t avh t vph t vp t vs a[18:0] v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il adv# oe# we# wait dq[15:0] in/out v oh v ol v ih v il v oh v ol ce# lb#/ub# t vp t avh t cw t wph t as t wp t wc t dh t dw data data high-z valid address t aa t bhz t aadv t cph 1 t co valid output high-z t cvs t olz t lz t as t blz t ohz t hz t aw t wr t bw undefined don?t care t oe t avs t cvs
? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trademarks of micron technology, inc. cellularram is a trademark of micron technology, inc., inside the u.s. and a trademark of qimonda ag outside the u.s. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified ov er the power supply and temperat ure range set forth herein. alt hough considered final, these specifications are subject to change, as further product development and data characterization sometime s occur. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory package dimensions pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 57 ?2007 micron technology, inc. all rights reserved. package dimensions figure 49: 54-ball vfbga notes: 1. all dimensions are in millimeter s; max/min or typical (typ) where noted. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 3. the mt45w512kw16begb uses ?green? packaging. ball a1 id 0.70 0.05 seating plane 0.10 a a 1.00 max ball a6 ball a1 ball a1 id 0.75 typ 0.75 typ 1.875 3.75 6.00 0.10 3.00 0.05 dimensions apply to solder balls post-reflow. pre-reflow ball diameter is 0.35 on a 0.30 smd ball pad. 54x ?0.37 solder ball material: 96.5% sn, 3% ag, 0.5% cu mold compound: epoxy novolac substrate material: plastic laminate 6.00 3.00 4.00 0.05 8.00 0.10
pdf: 09005aef82e41987 / source: 09005aef82e419a5 micron technology, inc., reserves the right to change products or specifications without notice. 8mb_4mb_burst_cr1_0_p22z__2.fm - rev. c 4/ 08 en 58 ?2007 micron technology, inc. all rights reserved. 8mb: 512k x 16 async/page/burst cellularram 1.0 memory revision history revision history rev. c, production . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/08 ? changed to production status. rev. b, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3/08 ? ?options? on page 1, ?part number chart? on page 9, table 7, ?electrical characteris- tics and operating conditions,? on page 30: added low-power option. ? figure 13: ?asynchronous mode configuration register write followed by read array operation,? on page 18: deleted clk and added ?(except a17)? under a[18:0]. ? figure 14: ?synchronous mode configurat ion register write followed by read array operation,? on page 19: added ?(except a17)? under a[18:0]. ? figure 15: ?asynchronous mode configurat ion register read followed by read array operation,? on page 20: corrected t aavd to t aadv. ? ?burst length (bcr[2:0]) default = continuous burst? on page 25, and ?burst wrap (bcr[3]) default = burst no wrap (within burst length)? on page 25: corrected internal address wrap to 00000h. ? figure 32: ?single-access burst read operation,? on page 40, figure 33: ?four-word burst read operation,? on page 41, figure 34: ?read burst suspend,? on page 42, figure 42: ?burst write followed by burst read,? on page 50: corrected timing paramter for lb#/ub# fl ling to clk rising to t sp. rev. a, preliminary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/07 ?initial release.

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